# file: axis_MxN_vio.xdc
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#/$Date: 2012/02/06 10:34:16 $
#/$RCSfile:  $
#/$Revision: 1.2 $
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#Created by Constraints Editor
 

    set src1 [get_cells -hierarchical -filter { NAME =~ "*probe_in_reg_reg*" && ( PRIMITIVE_TYPE =~ FLOP_LATCH.flop.*   || PRIMITIVE_TYPE == RTL_REGISTER.flop.RTL_REG || PRIMITIVE_TYPE =~ REGISTER.SDR.*  ) }]
    set dest1 [get_cells -hierarchical -filter { NAME =~ "*data_int_sync1_reg*" && ( PRIMITIVE_TYPE =~ FLOP_LATCH.flop.*   || PRIMITIVE_TYPE == RTL_REGISTER.flop.RTL_REG || PRIMITIVE_TYPE =~ REGISTER.SDR.*  ) }]
    set_false_path -from $src1 -to $dest1

create_waiver -type CDC -id CDC-4 -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter {NAME =~ "*probe_in_reg_reg*"}]]  -to [get_pins -filter {REF_PIN_NAME=~D} -of_objects [get_cells -hierarchical -filter {NAME =~ "*data_int_sync1_reg*"}]]  -user "axis_vio" -description {The path has combinational circuit. But from hardware prospective the design works perfectly and the signals crossing happen after a very long time from the source has the value.} -tags "1050886" -scope -internal

    set src2 [get_cells -hierarchical -filter { NAME =~ "*u_core_ctrl_reg/I_EN_CTL_EQ1.full_data_o_reg[2]*" && ( PRIMITIVE_TYPE =~ FLOP_LATCH.flop.*   || PRIMITIVE_TYPE == RTL_REGISTER.flop.RTL_REG || PRIMITIVE_TYPE =~ REGISTER.SDR.*  ) }]
    set dest2 [get_cells -hierarchical -filter { NAME =~ "*probe_in_reg_reg*" && ( PRIMITIVE_TYPE =~ FLOP_LATCH.flop.*   || PRIMITIVE_TYPE == RTL_REGISTER.flop.RTL_REG || PRIMITIVE_TYPE =~ REGISTER.SDR.*  ) }]
    set_false_path -from $src2 -to $dest2
    
    create_waiver -type CDC -id CDC-1 -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter {NAME =~ "*u_core_ctrl_reg/I_EN_CTL_EQ1.full_data_o_reg[2]"}]]  -to [get_pins -filter {REF_PIN_NAME=~CE} -of_objects [get_cells -hierarchical -filter {NAME =~ "*probe_in_reg_reg*"}]]  -user "axis_vio" -description {The path has combinational circuit. But from hardware prospective the design works perfectly and the signals crossing happen after a very long time from the source has the value.} -tags "1050886" -scope -internal

create_waiver -type CDC -id CDC-10 -from [get_pins -filter {REF_PIN_NAME=~C} -of_objects [get_cells -hierarchical -filter {NAME =~ "*/I_EN_CTL_EQ1.full_data_o_reg[0]"}]]  -to [get_pins -filter {REF_PIN_NAME=~CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ "*genblk1.xpm_cdc_async_rst_inst/arststages_ff_reg[0]"}]]  -user "axis_vio" -description {The path has combinational circuit. But from hardware prospective the design works perfectly and the signals crossing happen after a very long time from the source has the value.} -tags "1050886" -scope -internal

create_waiver -type CDC -id CDC-10 -to [get_pins -filter {REF_PIN_NAME=~CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ "*probe_out_all_inst/reset_sync_inst/genblk1.xpm_cdc_async_rst_inst/arststages_ff_reg[0]"}]]  -user "axis_vio" -description {The path has combinational circuit. But from hardware prospective the design works perfectly and the signals crossing happen after a very long time from the source has the value.} -tags "1050886" -scope -internal


